I'm new to the verification job and I have a problem.
I'm working with IFV version 8.2-p001 to verify a DMA IP.
The verification environment contains an RTL written in VHDL and testbench in Verilog and psl files in PSL/Verilog language.
Inside the Verilog testbench, I had created an instance of the VHDL IP but when I run IFV, it ignores the properties in the psl files where the vunit specified is the DMA.
Can anyone help me please.
Thanks in advance.
Good job for all.