I have obsered over time that the elaboration time of our design when simulating a gate-level netlist increases. Currently, it is even slower than the simulation time of most of our (directed) test cases. Is there any way to speed up this time? For example, is it possible to create an incremental snapshot with all hard macro models and primitives just for the DUT itself? The DUT does not change, only our testbench is different from test case to test case. This would prevent that ncelab always re-loads all simulation models from the inca pak file for elaborating DUT. From what I see in the elaboration log, loading the models takes most of the time.
If anybody has a good strategy how to shorten the elaboration time, please let me know. Thank you!