Hi, Do anyone know if there is a plusarg which can make NC to simulation signal only have two state 0/1 instead of four state 0/1/x/z. I wan't to speed up the simulation I wan't to if there is a way.Thanks!
I don't know of such a switch. However, I don't think the overhead in speed would be that noticable. I would think it would help more with memory. One way to check it out would be to use the SystemVerilog type of 'bit' instead of 'reg'.Tim