Hi,I'm using SI SigXplorer 16.1 and would like to simulate signals on a main board coming from a attached mezzanine card. What I have is the IBIS model from the signal source on the mezzanine card, a connector between mezzanine and main board and the design of the main board. What I not have is the design of the mezzanine card.Do you have some ideas, how I can simulate the signal integrity on the main board? Are there some tricks? Is it good/best practice to assign the IBIS model of the signal source directly to the connector, or can I add some 'virtual' traces between source and connector?Thanks for any idea or comment!