The "Electrical constraint set>static phase tolerance" in the constraint manager is what controls this. Click on the button that says"ns" and select "mils". Then type in the tolerance you would like. I usually type in 10 mils. Remember that "10 mils" will give you +/- 10 mils window. So any given diff pair may have 20 mil difference between the two trace lengths. The smaller the tolerance you give the harder it is to hit that "window" when you are sliding the traces around. You can also use delay tune in the single trace mode to "stretch out" the shorter trace so it is a closer match to the longer trace.
Hope this helps
In reply to padmaster:
I hope you are telling about Allegro16.5 or 16.6,is it possible in 16.3 or lower versions?
In reply to PRASH36:
I'm using 16.5 but I know it is the same back to 16.2. I don't have any versions older than that installed.
Thanks for your help, it is not quite the solution I was hoping for.
The trace loops back on itself, and I am trying to figure out how to have them equal lengths while keeping the same distance from each other across the whole trace. Maybe there is no automatic or eloquent solution for this.
In reply to TMCCANN:
The inside trace is always going to be slightly shorter than the outside trace. Unless of course you use delay tune to put a bump in the shorter trace. But at high speeds the bump can be worse than the trace lengths being slightly mismatched.
Yes, that's what I thought. I will just have to rearrange the components or figure it out.
What causes the requirement for both sides of a diff pair to be of equal length? I've never had a respected SI engineer show concern about a 5mm length difference under 10gHz.
Discussions of PCI-E 2.0 and 3.0 SI techniques focus on obtaining uniform dielectric properties along both nets. No mention of matching lengths on the pair.
In reply to Robert Finley: