When dealing with a match group in Allegro XL, it counts the length of the thru-hole barrel from the inner layer (where the trace connects to the barrel) to the outer surface of the PCB (component mounting side). Normally this is a good thing to do because it makes the estimated "signal path length" more accurate. However, when using press fit connectors, the "compliant pin" makes contact somewhere in the middle of the barrel (40 to 60 mil down), not on the outer surface. So a trace touching the barrel on an inner layer actually has less delay than a trace touching the barrel on the top layer. Thus the estimated length Allegro XL computes is wrong. It may only be wrong by 5-8 ps, but when your skew budget is only 20 ps total, I can't give up 8ps error at the connector.
Any advice for dealing with this?
Have your tried using a negative pin_delay value on the pins that need this compensation?
In reply to fxffxf:
Hi fxffxf,Yes, I can use negative pin_delay to correct this. It is a manual process though, for each pin I need to look up what layer is being used, determine the correction factor (based on stackup) and enter it as a negative pin delay into the constraint manager. I can do that for a handful of critical nets but it will get tedious fast. So I was wondering if there was a better way.
Is this after allowing for skew due to weave? After skew due to inherent connector skew? And are you *sure* that you are computing the propagation velocity of the barrel correctly? If the barrel allows a non TEM mode to propagate then all of your estimation (in Cadence and most tools) is garbage. Lots of papers out there on skew mitigation. In fact I think I have one :) And don't forget barrel capacitance and how it affects delay.
There is a good SI forum over on yahoo that might be able to give you about 100 or more opinions on this.
In reply to redwire:
I agree, estimating propagation through the via barrel is challenging. I would be better served by using the same layer to route all the nets in this critical match group. This is why its best to define requirements before layout begins, not after the first batch of boards has been built 8-)