I'm using Allegro PCB Editor 16.3, kind of new to it but I have plenty of experience using OrCAD Layout. I.e., I know what I want to do, but not how to do it in PCB Editor.
I'd like some help with the following problems, one or (preferably) more of them:
In case 1, I have a 3-pin symbol in the schematic, that is to be connected to a 4-pin, through-hole footprint (the physical component, a TO-220, have pin #2 and the heatsink connected internally). I have placed a static solid (non-dynamic) shape on the TOP layer, that includes both the electrical pin #2 and the mechanical pin. This works but produces DRC errors ("Thru Pin to Shape Spacing", which I waive in the board editor). However, there must be a better way to do this. (I don't want to introduce a fourth pin in the schematic symbol.)
In case 2, I want to place a copper area on the BOTTOM layer beneath the TO-220 mentioned above, and connect the two with thermal vias. Of course I want the bottom copper to remain beneath the actual component, even if it is moved.
In case 3, I tried including a "anti-etch ALL" shape, in both the symbol editor and the board editor, but the dynamic copper fills still came to within the global clearance limit. I solved the problem by creating voids in, or modifying edge contours of, the dynamic ground plane shapes, but this will of course cause problems if the components are moved (and if I forget to update the planes). Must I somehow give the anti-etch shape a higher priority than the dynamic fills?
In case 4, I have a 6-pin DPDT switch that I use as a SP3T switch (by shorting two of the leads). The symbol have relatively gigantic holes in the PCB, since the actual component is supposed to be panel mounted, not TH mounted. So I included smaller-diameter holes near each electrical pin, defined as mechanical pins, to make it easier to solder cables to the board. All four electrical pins are connected to the corresponding mechanical pin with a solid copper shape on an etch layer. The four remaining mechanical pins are connected by a similar shape (and are automatically attached to "Dummy net"). However, when this symbol is placed on a ground plane, the ground plane shorts all four mechanical pins. (The electrical pins and the corresponding mechanical pins have the global shape clearance distance.)
[Edit: The schematic SP3T symbol is a 4-pin component, so I could solve this by making the schematic symbol a six-pin component, to match the actual footprint. But this forces the schematic designer to manually connect the two remaining pins. It would also clutter the schematic. My non-ideal solution so far is to make voids in the ground plane around each SP3T switch.]
1. DRC errors are always produced in the symbol (DRA file). The DRC's are cleared when you place the symbol into a board file and import the netlist. The shape will take on the netname of the net connected to the pin. So If pin 2 is connected to VCC that would be the netame of the shape.
2. You can window select the items you want (check find filter for more control) then use RMB (right mosue button) Add to Group, enter a name and OK. Then make sure only group are checked in the find filter (or RMB super filter) and move the group.
3. Add a shape to the layer Route Keepout / All or layer specific.
4. If they are mechanical pins then they WILL ALWAYS be voided from a net. Check that the shapes are dynamic and that the shape to clearances are set. If they are electrical pins and they do connect (but you don;t want them to) then add a property to the PIN (RMB - Property Edit) called DYN_THERM_CON_TYPE and set this to NONE.
In reply to steve:
In reply to Johnny Nguyen:
I don't remember if it is available in 16.3, but in 16.6 you c an add the property "Via allowed" to the route keep out shape to get the results you are looking for I believe.