I have a design that includes a TS201 DSP, SDRAM, embedded FLASH memory and FPGA(virtex4). I want to connect the data wires to each of them with a star topology. Each of the ICs has the capability of transmitting and receiving signals so all the pins are transceivers. I have applied a series termination to all pins. For example for dsp a series resistor of 18ohms, for SDRAM a series resistor of 22 ohms, for FPGA and FLASH memory again 22 ohms. The results are pretty good with sigxplorer but I want to ask if this kind of termination is used practically in the designs.Else what kind of terminations can be used.
I want your advices. Thank you very much
Hi Ahmet,In star topology, series termination on all drivers is not practial. Generally in Star topology , AC termination is good and easy for routing. AC termination location is near of the SDRAM not other processor or flash. But simulation is required. I just define only starting point. If you need more help about SI, I want to discuss your topics. email@example.comFERHAT YALDIZSI EngineerTURKIYE
Hi Ahmet,Assuming all your tranceivers are high Z when they are receivers, you might like to consider a flyby topology.For example:Terminator. |DSP |SDRAM |Flash |FPGA |Terminator.The signal from any device as a driver will propagate in two directions. Reflections will not occur as the signal will stop at the terminators at each end.Of course you won't be able to replicate this exactly, play with keeping stubs from the bus to each chip short (so that they don't from T'd transmission lines) and with raising the impedance of any stubs to reduce reflections from the point at which the signal must branch two.Hope that helps
Hi Vealmic,Thank you for your suggestion. I have tried a couple of things with your suggestion topology and realized that it can work. As far as the stub lengths shorter the simulation results are good. I have tried RC termination on both sides. Monotonic result for SDRAM is failed . Is this important I don't know. What can you suggest for termination? I can send you the topology files and ibis files if you want to look at.With my best regardsAhmet OZSOY