Hi, First post on here. Im in the latter stages of a new design (first one on conceptHDL). I previously used PADS and an engineer that has since left generated some VBscripts to check schematic naming, net loads etc. Im looking to duplicate this in ConceptHDL (basically some additions in connectivity checking to the Electrical Rules Check). The kind of things Id like to do are as follows:Run a script(s) that will drop a report file out telling me :1) Net names that are only on one page of a design including net name and page reference.2) Bus loading - I would like to be told what the number of nets is hanging off each bit in a bus?3) Something to spot typos - where two net names are similar but say two characters are different?4) Something to go through all the components in my schematic and where there is a property called 'FITTED' set the 'Value' to 'Visible' ?I may be after the moon on a stick here but any help or pointers as to how go about this would be good.Thanks,Neil.
once you packaged the design (export physical) all the information is available in the packaged folder files ( pstx*.dat).It requires to parse those textfiles but you can extract all such info from there i.e. using an Perl script which can run in Windows and Linux. This would solve 1,2 and 3.For item 4 you could write an backannotation script or an script/skill inside ConceptHDLscript: set next a find "fitted*" disp value aTobias
Hi,Can you confirm, whether you could accomplish any of the schematic checking?...Will you please share the techniques you followed?Thanks,Karthik