Hello.I'm in the process of verifying what are the necessary steps to achieve fully placed & routed design using First Encounter - I've read few tutorials and assembled the following steps:* Design import (sythesized verilog file, SDC etc.) * Floorplanning* Power planning (power rings,power stripes and routing)* Placement* Pre-CTS timing optimization* Clock tree synthesis (creating specification, specifying it and the actual clock tree synthesis)* Post-CTS timing optimization* Routing using NanoRoute* Post-routing timing optimization* Filling (fillers,metal fills)* Verifying* Exporting resultsYour input on the validity of those steps and ideas for possible needed changes would be much appreciated.Thank You,Adi.
Hello Adi,I think you have the major steps outlined.Depending on the size of your design you may spend time in the prototyping / floorplanning step. In my experience the more time you spend in this part of the flow the more push-button the rest of the flow is. The macro placer is very useful for macro placement, estimating module and partition placement as well as congestion analysis and IR Drop analysis. You can generate multiple floorplans and rank them based on user criteria. There are additional options for controlling the placement of the memories.This feature (command is planDesign) will automatically create a power structure if desired based on your design power requirements, next run a quick placement (cluster place) and finally run global routing. The flow is as follows:setPlanDesignMode -autoPowerPlan 100 -congAwareplanDesignThe "100" specified above in setPlanDesignMode is an estimate power requirement of 100mW. You can also add -powerAware option to have the tool perform an IR Drop analysis if used planDesign will automatically overlay the floorplan placement with an IR drop map. Regards,Elvis
In reply to archive:
In reply to eklikeroomys:
Floorplanning is done in Encounter.
For a mixed-signal design where a schematic rather than a Verilog netlist is the starting point, Virtuoso-XL can be used to convert the schematic view to a layout view using a flow involving the V-XL command: Generate Physical Hierarchy.
After floorplanning in V-XL, output a DEF file which captures your floorplan. The LEF views of your IPs along with this DEF file can be imported to First Encounter where you continue in the recommended FE flow.