In ETS I am getting the same cell delay for a cell BUF when I the design is set at 25C and 110C. Ideally I should see the delay increase. I saw the cell in the exactly same path in both the designs. What could be the explanation?
Make sure your timing library has k-factors defined so the tool knows how timing should be scaled based on PVT. For example, the timing constraint equation for setup rise is.
rise_constraint * (1 + delta_voltage * k_volt_setup_rise)* (1 + delta_temp * k_temp_setup_rise)* (1 + delta_process * k_process_setup_rise)
Hope this helps!
In reply to wally1:
I have done temprature scaling and am seeing the the effects of temprature scaling in the total delay, but for one or two cells in the path the delay is not increasing at all.