A low-power expert, Sandeep Mirchandani from Broadcom, will present a paper at CDNLive! Silicon Valley, "Low Power Design Techniques That Don’t Work". Abstract: There's always a risk that some new design modification introduced for low power doesn't actually end up saving power. Worse still, it could cause the chip to fail. This session will catalog some common problems with low-power structures and illustrate how to catch them. The focus will be on advanced leakage control techniques such as power gating. Many things can go wrong in the implementation of power shut-off. There could be design bugs, such as the failure to isolate before turning off a source block. There could be tool bugs, like connecting an always-on buffer with a switchable power domain. Most problems lie in the gray area between these two extremes: where a tool makes erroneous assumptions based on incomplete design intent. This paper will show examples of these bugs. Encounter Conformal Low Power and Incisive Unified Simulator are some of the technologies used to ensure these types of bugs don't cause failed chips. Many of these example problems are solved by having clear communication of low-power intent. This session discusses how to capture low-power design goals using the Common Power Format (CPF). Formal constraints coupled with design rules significantly reduce the risk of incorrectly implementing power gating techniques.
this excellent paper will be available to CDNLive! Silicon Valley attendees only until January 2008. You can register this week for the event and still receive the early registration discount.
Can someone please send a copy of this paper ? Thanxhg
You can find it herehttp://www.cdnusers.org/CDNLive/SiliconValley2007Proceedings/tabid/419/Default.aspx?topic=Digital%20Implementation It is the first one on the page.Luke