I would like to understand the definition of lp_default_toggle_rate. The default rate is 2%/ns. So, if I interpret it correctly, for a design that is 200MHz (5ns cycle time), the toggle rate per cycle is 10%; and for a design that is 100MHz (10ns cycle time), the toggle rate per cycle is 20%.
Do I interpret the definition correctly? Please kindly confirm or clarify. Thanks.