I am using cadence "Soc Encounter 5.2" in which i imported "design.v" & "design.sdc" from RTL compiler 5.2.
How and from where to get "design.io" file to import in "IO Assignment" file option in the basic form of "design import".
Hi vlsi_dude,The IO Assignment file is an optional input. It can be used to instruct the tool where to place IO pins (in a block level design) or IO cells (in a chip-level design). If you want the tool to determine these locations automatically, you can leave this field blank.More typically, the locations of IO pins or IO cells are brought in after the Design Import step via a DEF file or a First Encounter ".fp" file. These floorplan files can also define things like the design size, the power grid, and FIXED hard macro locations. If you don't have a DEF or a .fp file, the tool will automatically determine a design size depending on the area of the instances in your Verilog netlist, and when you run "placeDesign" your IO pin locations will be automatically determined. If you're working on a block within a hierarchical design, First Encounter can generate the DEF or .fp file. The right thing to do depends what stage in the design process you're in (early on making estimates vs. late in the process and requiring detailed implementation) and whether your metodology is more tops-down or bottoms-up.Hope this helps,Bob
to add to Bob's comment. You can write out a sample copy of the design.io after you have "create a floorplan" (you need to fill in the blk size or util., aspect ratio...).
I'm working with chip level design which have only pink colured blocks.I'm in the early in the process i.e just after design import.
Methodology followed is tops-down.