Hello,When a timing arch of a cell has COND expressions, what delay value of these conditionalexpression is used for setup and hold analysis?Considering the example below, what delay value would be used by, e.g., CTE to report delay of this cell considering timing arch C -> Q?#####(CELL (CELLTYPE "ON21LX1") (INSTANCE gbl_slave_test/g310) (DELAY (ABSOLUTE (IOPATH C Q (0.076::0.076) (0.047::0.047)) (COND ((A==1'b1)&&(B==1'b1)) (IOPATH C Q (0.076::0.076) (0.047::0.047))) (COND ((A==1'b1)&&(B==1'b0)) (IOPATH C Q (0.078::0.078) (0.057::0.057))) (COND ((A==1'b0)&&(B==1'b1)) (IOPATH C Q (0.079::0.079) (0.076::0.076))) (IOPATH B Q (0.106::0.106) (0.092::0.092)) (IOPATH A Q (0.082::0.082) (0.076::0.076)) ) ) )#####Can anyone help me?Regards,Cristiano.
the worst case number will be used (in this case 0.079 for rise & 0.079 for fall) unless you have a set_case_analysis statment in the sdc file to set the state of pin A or B.li siang
Thanks again lisiang.Will timing analyzer use worst case delays for setup analysis and best case for hold analysis?What is the purpose of the delay values in the right side of "IOPATH C Q"?What delay value will be used in case of ((A==1'b0)&&(B==1'b0))?Cristiano.
Sorry i was wrong about the 0.079. If logic state of A OR B is unknown. STA uses the IOPATH number, 0.076 for max path and 0.047 for min path. If A=1 && B=1 (set_case_analysis) then max path check will use 0.076 and min path check will use 0.047. Typicallu max path is for setup check and min path is for hold check.
One clarification dsantos,Most tools will use ALL arcs, and take the max delay of them(min for hold checking). If, however, one of the inputs of the gate was a constant(hard-wired or case analysis), then arcs whose "COND" function resolved to 0 are disabled. Also, if the constants on the gate inputs narrow the choice of COND expressions down to a single one, then the default "COND-less" arc is disabled. Hope this helps.regards,gh-