I am new to this soc encounter. Currently i am using bottom up approach for my digital pnr. There are 2 submodules in my design, Module A and four Module B. I have done PnR for each submodule and saved the DEF and GDS2 files.
The final top level will have integration with analog block. That is Module B will be connected to Analog block. Module B + Analog block will be arranged in row and column manner.
As of now, i would like to simulate just my digital block. At my top level netlist, i have instantiate Module A and four Module B. So it means i wanted to have Module A and B as hard macros. At the top level there will only be wires (control signals and clock) that connect between Module A and B. All the standard cells are already routed in both modules.
My questions here:
1. Is it possible for me to load the DEF files of the routed modules ( A and B) and make sure at that the top level instantiation, it will contain the routed module?
2. Should i load the DEF file or LEF file or GDS file for the submodule at the top level? How do i save the LEF file for the routed submodules ( A and B)?
Ok hope to hear some response
You use lef at the top level to do toplevel routing. You an generate lef file either by using the virtuoso abstract generator or you can do lefOut