In our design we have IO fillers with blockage for the IO ring power & ground stripes, and IO pads with pins for the same busses. When placing fillers between the IO cells, we see short violations between the pad pins and the filler blockages (see attached image). How can we fix or ignore these violations?
The LEF for the IO filler and pad looks like:
MACRO IOFILLER ... OBS LAYER M3 ; RECT 0.00 78.50 5.60 104.06 ; ...MACRO IOPAD CLASS PAD ; SITE IO ; PIN VDD! DIRECTION INOUT ; USE POWER ; PORT LAYER M3 ; RECT 0.00 78.82 75.04 83.58 ;..
Link to GUI image: http://i42.tinypic.com/33di5jc.gif
Thanks in advance,
To avoid shorts you have at least 2 ways:
1. If blockage represents actual wire in the filler (not pad ring) then shorts are valid and you need to resize pad pin in IO cell to meet spacing (maybe you need to consider width-depended spacing rules).
2. If blockage comes from pad ring wires in the fille, then you need to define related pins in filler cell. This will close pad ring connections and violations will gone.
Hope this helps.
In reply to mikhail:
I am facing the same issue right now.
can you please elaborate what should i check?
In reply to ErezBS: