Hi all,Please can anybody tell me about how to calculate number of straps,power ring widths for a particular chip( if possible give some examples).And also give me the info about how to reduce the power dissipation while doing power planning in the physical design.I am waiting for the solution........
good qn. I know there is some formula out there bu this is what i do. 1. look at a previous design which is similar in size and same process if available. 2. once you have a basic power structure built, you can run FE's statistical floorplan mode power estimation/ir drop estimator. you have to know the pad locations of the pg pins, and the clock toggle factor/freq . (look at the doc for help). 3. if you dont meet ir drop spec at this stage or you barely meet it, you should provide more stripes or increase ring width etc. i generally try to meet half of the ir spec limit in floorplan stage. power dissipation is design related. all we can do is ensure all cells get a voltage close to the supply voltage. we cannot reduce power diissipation. you also need to feed in a realistic expected power no for step 2 to be accurate.
Hi pjayasekharan,Thanks for giving me the reply.Actually i want to know the formulae for calculating all these strap withs,core ring widths etc in general.(not related to particular technology).Please can you give me the info.Thanks in advance.
There is a good appnote in sourcelink. Check it out.Sanjay
hi ssunder,I am not able to find the link.Can you please send me that source link.Thanks in advance.
hi i am not able to access the material. can someone mail it to me @ email@example.com