I got an IP from vendor. Due to design change, some part of the IP are not needed. Since it is time consuming to ask the vendor to remove those flops, I wish to do it in synthesis. I tied the unused part IP clock port and reset_n port to 0. And I want RTL compiler remove those unclocked/always reset flops.I have try set_attribute optimize_constant_0_seq true unclocke_register
but it doesn't work. Can anyone help me? thx!!
RC should have removed the flop you mentioned by default. The setting you specificed is default after all. If that part of the IP is truly dead logic, then RC will more than certainly remove it, even without you having to do anything. Please provide some sample code and maybe we can better help you. I am guessing that either there are still functionality tied to transitive fanin and fanout in that logic or logic is preserved / dont_touch somewhere in your implicit or explicit constraints. I suggest you provide a short RTL example or contact your local AE
In reply to grasshopper:
Thx for your reply. The IP has multi AHB master ports, we remove 1 master so one of the AHB master ports related signals are all tied to 0 (ex: AHB7_HCLK, AHB7_HRESETN....)
I think there maybe some input ports related to those registers are not tied at 0.
But what I am curious is that I am sure the clock port(AHB7_HCLK) is tied to 0 and reset_n (AHB7_HRESETN) port is tied to 0.
My question is that I think make CLK and resetn tied to 0 is good enough to guarantee those registers are staying in their reset state, which is constant.
Will RC treat them as constant flops and remove them since they are always reset? Or I need to ensure all the logic related to the flop's Data port is static (that's kind of a huge work)?
In reply to tompy:
RC tends to be pretty aggressive about removing useless logic. In your shoes, I would simply put together a testcase RTL and validate the opitmization as you described. 10 lines of HDL will go a long way. I do not think you need to tie the clock to 0 for one thing.
after a lot of trial run, I finally find the root cause. I set boundary_opto attribute to false, which will disable constant propagation across hierarchies, thus avoid RC to remove those unused registers. After set boundary_opto to true, those registers are removed.
BTW, either tied clock to 0 or tied rst_n to 0 is good enough to let RC remove thus registers.
sorry it took a while to get to the bottom of it but happy to hear it worked as advertised. Thanks for sharing your findings with the greater community. It always benefits others users.
On a related note, boundary attributes can be applied at the instance/subdesign level if needed.