I developed a design based on VHDL-2008 standard, I can compile it and simulate it pretty fine using NClaunch and SimVision, respectivly.
However, I am not able to synthesis the same code using RC.
I am using Cadence 5 flow with RC v10.1.
What is your recommendations to overcome this issue.
In waiting for your constructive feedbacks.
I suggest you contact your local AE and identify the VHDL-2008 constructs you are seeking support for. VHDL-2008 is not fully supported yet. In fact, I would caution you most EDA tools out there do not FULLY support VHDL-2008