In my design with 5 cores I have a Placement blockage around each core. This was suggested by Kari to stop sroute from connecting all follow pins together. But now CTS and also nanoroute stops routing all signal that run from the cores trough the blockage to the IO pads.
I though its a placement blockage and not a routing blockage. Trial route works fine, but produces a lot of violations. What can I do to
allow nanoroute to pass trough the placement blockage?
I think it has to do with the following error:
NET $net is marked as fully connected but pin $pin of instance $instance is not yet connected.
This is repeated for all toplevel nets going to the IO cells. How can I reset these nets, so that they will be routed again?
In reply to Kari:
In reply to schnufff:
It sounds like your IO LEFs don't have physical pins defined. If you zoom in to the I/O cell, do you see pin shapes? You already said you checked the LEF...
To try routing a net by hand, see the "Editing Wires" chapter in the User Guide.
Are those nets considered "SPECIAL" nets? (If you output a DEF, do you find these nets in the NETS section, or the SPECIALNETS section?)
Try these things and see what happens next - hard to debug from a distance, but hopefully we can get to the bottom of it.
also, check out this blog entry for wire editing:
after reading the manual, I am able to route the wires manually without problems. I also can see the pins of the IOs at layer M2 and M3.
There is no attribute like special/power/whatever set to the wires. The lef files of the cells have CLASS PAD INOUT, the Pins have USE SIGNAL, and a PORT definition with the metal layers. In the def file, in SPECIALNETS are only the power nets and in NETS are all the signal as expected.I am unshure if tis an error within the lef files are some tool set these "fully connected" attribute wrong. Trial route is connecting the IO-wires correct! So the physical pins seem to be there.