Hi, I encountered a problem with the impementation of a digital block using an RC-Encounter-Virtuoso flow.
When I synthesize the block, the generated netlist/schematic uses one cds_thru block to connect two different pins to a single net. Encounter does not have any problem with this, and then generates a layout connecting two pins to the same piece of metal. So far, so good.
The problem appears in Virtuoso, because DRC (end then Extract and LVS) fail complaining that two pins are connected to the same net.
I am using NCSU CDK 1.6 beta.
Can someone provide any workaround?
I imagine this case of having a netlis with cds_thru connected to a pin is not uncommon. Is it then a problem of the DRC being too restrictive for this CDK?
Thanks in advance.
One net name = one signal route = one port name @ one level of layout hierarchy .... that's the rules.The only way to logically legalize this situation is to break the "one signal route" with at least a buffer to create two unique net names.If the different pins are connected to the same net through an "assign" statement try setOptMode -bufferAssignNets true.Otherwise ecoAddRepeater -term <port2> might do the trick, I have only used it on a cell term not a block port.As a last resort use the "Interactive ECO Commands", it will take a couple of tries to script it correctly.