I need a clarification for the below issue. I have a 550k+ sinks for clk_sys. To get, better skew & insertion delay values. I found out the clock gating cells & mentioned those output as "AutoCTSRootPin" lets take CLK_GATE as clock name & has some 400k+. I mentioned those in the intial portion of the ctstch file and later my main clk "clk_sys" comes up. so, it will build for "CLK_GATE" 1st then it comes to clk_sys.
As the result, am getting better skew & insertion for CLK_GATE But for "clk_sys" am getting worst values. My question is, once clock tree is built for "CLK_GATE". when it comes to clk_sys tree. Whether it will re-build "CLK_GATE" tree again?
Hope my quesion is clear. Plz let me know any more brief explanation needed.