I've ran into a particularly a troublesome error while running SOC Encounter.
I'm currently implementing a design starting from behavioral verilog, synthesizing using Design Compiler
and then running place and route using SOC Encounter.
The problem is that the verilog netlist produced by SOC Encounter does not seem to match functionally with the
behavioral verilog and synthesized verilog. The synthesized verilog works fine, but the place and routed design
produced by encounter is functionally incorrect when simulted under the same conditions.
Has anybody experienced anything like this, and does anybody know how to ensure that Encounter produce a functionally
correct design? My guess is that encounter does something wrong while re-synthesizing during timing optimization. This is an important issue.