New to this area, I have two questions that need your help.
1st, when I get the power analysis from Cadence Encounter RTL Compiler, It automatically shows Leakage, Internal, Net and Switching Power of the generated schematic. But then I get comfused, under which input pattern does the Compiler infer all the power values, especially switching power, since it's directly related to the frequency of input?
2nd, what's the difference between Leakage Power and Internal Power? And does Net Power means power consumed from the interconnect? I get confusion about these terms
Thank you very much for your notice and help!
1.Generaly basic power information come from .lib .like how much leakage when cell have different-different logic.for each cell in stander cell lib. and other information come from collapsed/port view of standered cell and macro.
2.Two type of power in CMOS :
a.dynamic power(switching power)
b.static power(internal power)
And leakage power is leakge of both dynamic and static IR drop.
For detail of CMOS power:
In reply to ajay01:
In reply to Haoxiang:
1.leakge of dynamic power is not only short circuit power but it is also calculating ir drop during Charging and discharging of load capacitances.
so dynamic power leakage= short circuit power+ power dissipation during Charging and discharging of load capacitances.
2.Yes net power related to static IR drop.its independent of switching activity means dynamic power.
In reply to zhaojun:
1.As i mentioned,Dynamic power is the sum of two factors: switching power plus short-circuit power.Switching power is dissipated when charging or discharging internal and netcapacitances. Short-circuit power is the power dissipated by an instantaneous shortcircuitconnection between the supply voltage and the ground at the time the gateswitches state.Pswitching = a .f.Ceff .Vdd2Where a = switching activity, f = switching frequency, Ceff = effective capacitance,Vdd = supply voltagePshort-circuit = Isc .Vdd.fWhere Isc = short-circuit current during switching, Vdd = supply voltage,f = switching frequencyAs we will go ahead in technology we required chip should work faster means frequency will increase.So as shown above equation dynamic IR drop increase.For that we are using Low Power Techniques and CPF flow.So RTL compiler set frequency based on requirement and leakage calculation and technicians which will be used during Physical implementation.2. In standard cell library that defines as below:consider its a buffer.Then it will define leakage power when logic A and !A.And internal power At pin A.full table.Like that for all std. cell power define with different logic.
I am working in physical design.so i dont have idea about synthesis mode and input type..
If any fundamental question then i can help you.
I am facing problem while removing short violations in encounter while performing geometry checks. Can u kindly provide me the solution for this. Looking forward to hear from u soon