I made several behavioral designs in Verilog that use tri-state buffers. Structural Verilog from Synopsys uses the TSGEN function to implement tri-state buffers, but the tech library does not seem to have TSGEN implemented, and attempting to place & route results in the tri-state outputs being unconnected. How do I get on the path to learning how to implement the TSGEN function in the tech Liberty file? Is that even where TSGEN is supposed to be located? I realize that learning this may take a long time. That's fine. I just don't know where to begin.
An alternative would be to write a tri-state standard cell (it's only 8 transistors) and edit the structural Verilog to call this cell instead of the TSGEN function. If I were to do this is it possible to tell Synopsys to use this new cell instead of manually having to convert TSGEN to the tri-state cell each time?
Any input would be appreciated.