Can anybody help me to integrate Specman verification component(uVC) in system verilog environment.
Urgent. If anybody knows any link pls share it.
There are many options for integrating e and SV together in the same testbench. Rather than trying to list them all here, I think it would be more productive if you contact your local Cadence AE who will gladly help you.
If you have a UVM or OVM testbench it's easy, via TLM ports, to connect a complete mixed language environment.
Anything else requires a more bespoke solution depending on your exact requirements, but there is a lot the tools can do to help.
In reply to StephenH:
In reply to sujntto:
I see you're now connected to your local support guy, so we'll take the discussion offline.
Perhaps once you're up and running though, you'd be kind enough to post a summary so other users can benefit from the experience?