Firstly you should not be using tick accesses these days. You should be using simple ports instead, as they have better performance and give less flow problems such as the VHDL/Verilog binding that you're seeing.
dma_done_w : in simple_port of bit is instance;keep dma_done_w.hdl_path() == "~/ve_top_tb_sn.DUT.ve_core_inst.pss_top_inst.pss_ring_inst.pss_core_inst.pss_arcss_core_inst.ipss_dma.done_w";keep dma_done_w.agent() == "Verilog";event collect_cover_done_e is rise(dma_done_w$)@sim;
This gives you other benefits because each port in a unit can have a different language agent set, which avoids the limitation of tick accesses where the entire unit has only one language agent.
Now, the other common mistake people make is thinking that they don't need to load their e code when generating the stubs file.You MUST load your e code before generating a stubs file, otherwise the simulator doesn't know which RTL signals you wish to connect to. This is important because the simulator tends to optimise away some signals (e.g. feed-throughs) to improve performance. It must know during elaboration that you want access to the signal, and the stubs file tells it that information.
After generating a stubs file, you only need to regenerate it if the signal connections change, i.e. adding ports or changing hdl_paths.
In reply to StephenH: