I have an assertion along the lines of :
assert property( @(posedge clk) A |-> B );
When I run this on Cadence, I get that the assertion failed. Looking at the waveform (counter example), it shows that when A occurs on the negedge of the clock, Cadence is still checking to see if B happened. And when it doesnt, says the assertion has failed. Why is this happening and can it be fixed?
the SVA property you paste is only evaluated at the posedge of the clk, it cannot cause a failure at the negedge of clk. When you say "SimVision Assertions" this implies that you run either our Simulator ncsim or our formal tool iev. Which?
Can you share the log and waveform with us?