99% of the issues like this are due to race-conditions in the Verilog model. If you have access to an account on support.cadence.com, do a search for "Race Conditions". There is an Application Note that explains what might be going on in your simulation. If you have an issue where the order in which events occur in a timestep affects the simulation results, removing more optimizations may not solve it since Verilog doesn't enforce any particular event order for its signal transitions.
In reply to TAM1: