In my SystemVerilog environment, I have an array of a class typefor which I need to customize instantiation parameters for each class in the array. With all classes the same, I can do
my_class #(.PARAM1(32), .PARAM2(8)) classes;
However, I can't figure out how to customize the PARAM1 and PARAM2 parameters for each specialization. Is this possible?
I don't believe it is legal to have different parameterizations for an array in SystemVerilog.
You have atleast 2 options that come to mind:
1) Use variables in classes that you can initialize, configure or constrain to different values to model different behavior. I suspect that your params are affecting data types, value ranges, etc. so this may not be viable.
2) Use different array identifiers to group classes with same parameters.
In reply to umery:
In reply to benbuchanan: