I'm assuming that you're referring to UVM-SV since you mention interfaces. If you'd been talking UVM-e it's easy, just enable coverage of checks in Specman using the "collect_checks_expects" option.
For SV, Incisive doesn't currently collect coverage of immediate assertions in classes, though it's something that we're planning to do. As such, it's not possible for Enterprise Planner to show you the SV assertions, since the simulator didn't put them into the coverage model.
I recently wrote an application note that shows a fairly straight-forward way round the limitation. You can read it here and see the example code: http://support.cadence.com/wps/mypoc/cos?uri=deeplinkmin:ViewSolution;solutionNumber=11784374
In reply to StephenH:
Yes I was referring to UVM-SV. I implemented your way round the limitation and I was able to map check in the Eplanner. My way round the limitation was to introduce an interface with the signals that are not actually connected to DUT but just used as auxiliary signals which are set from the monitor and then I implemented assertions on those signals in that interface.