I am migrating my project from Synopsys VCS to Cadence INCISIV. My
project uses SVA library Cadence's library ial can not be used in this
case. I get the following error when I compile the SVA library (VCS) in
(../design/asserts/sva_cg/assert_dual_clk_fifo.v,541|39): Illegal use of
sampled value function outside concurrent assertions and procedural
assign enq = $sampled(i_enq);
If i dont use the SVA library. The assertion properties are not found even if i use Cadence ial library instead.
Is there someway to compile using VCS SVA for the assertions in Cadence ? I am using the irun command.
What is the cadence alternative for VCS SVA. Some of the assertions are specific to Synopsys like assert_dual_clk_fifo.v .
In reply to Maisum:
I have no idea what's in the proprietary SVA checker library from Synopsys, but from your example of the error you got, it looks like the SV code is not legal, which is why you can't compile it in Incisive. As far as I know, $sampled cannot be used in a wire assignment according to the LRM.
As for what Cadence does offer, the Incisive Assertion Library includes ial_mclk_mport_fifo which is a multi-clock FIFO verification component. Full details are listed in the cdnshelp application.