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Can I force or probe a signal in vhdl module from verilog top testbench?I heard some simulator has its own way to do that easily, can you give me a example code to do that with ncsim?
Hi Hubert X,I will reply to this question in a separate Thread, since this is the wrong thread.F.
I have a problem in taking the ratio of two node voltages (v(1)/v(2)) in AC Analysis(sweep). Using ABM2(VALUE),yield results which are too large(1e30). Obviously I'm doing something wrong. Any help in the form of comments, papers,or books would be appreciated.
Trapper,this is not the appropriate forum for your question and since it is not a new thread, I cannot move it to the correct forum.If this question refers to AMS, please re-post your question on the Custom IC Electrical Design forum.If this is a Verification simulation question, please re-post to the Verification forum, Simulation, Acceleration, Emulation.Administrator