Welcome to the Verification Formal Analysis forum; a place to keep your finger on the pulse of the latest software developments and happenings in the areas you care about most. Get to know the experts, both inside Cadence and in our worldwide Verification user community. Ask your questions, get answers, and share best practices. Tell us what's on your mind...other users want to know what you think. This forum is not intended to be a substitute for Cadence customer support and/or documentation, but we do believe that it will be helpful and a way to tap into vast knowledge that exists in our user community. Of course, any software support, documentation and installation issues should also be directed to your preferred Cadence support channels. File attachments must use one of the following file extensions:.doc, .pdf, .html .zip, .il,.jpg,and .gif. Size limit on the attachments is 750KB. If you have questions or need help with attachments, send an email to email@example.com Administrator, cdnusers.org
Can I force or probe a signal in vhdl module from verilog top testbench?I heard some simulator has its own way to do that easily, can you give me a example code to do that with ncsim?
Hi Hubert X,I will reply to this question in a separate Thread, since this is the wrong thread.F.
I have a problem in taking the ratio of two node voltages (v(1)/v(2)) in AC Analysis(sweep). Using ABM2(VALUE),yield results which are too large(1e30). Obviously I'm doing something wrong. Any help in the form of comments, papers,or books would be appreciated.
Trapper,this is not the appropriate forum for your question and since it is not a new thread, I cannot move it to the correct forum.If this question refers to AMS, please re-post your question on the Custom IC Electrical Design forum.If this is a Verification simulation question, please re-post to the Verification forum, Simulation, Acceleration, Emulation.Administrator