Verilog question (Tripoli – Lebanon)
I nead a help for a verilog simulation program:
I am trying to do a real numbers multiplier in verilog simulation code using ModelSim simulator (without schematic).
The Problem is that Verilog doesn’t accept to define an input as real (register) and when I try to use intermediate real registers before multiplying and put the result also in a real register; verilog around them to integers!!!! L
I am very sad…. :’-( Plz any help?
Ihab – Lebanon (University of Balamand)
take a look at $bitstoreal and $realtobits