Referring to recent thread on www.verificationguild.com, topic:Assertion failures and pass/fail status Adam asked:-------Any word from Cadence on the ability to substitute your own $error() routine ?
This definitely would be nice.-----I know that atleast one other vendor allows it easily. What about NC? Or is there any other easier way to keep a count of all SVA errors and declare PASS/FAIL at the end? How does URM handle this? This is a very common problem as many RTL engineers write assertions and it is hard to ask them to keep following a standard action-block syntax. Also with IPs etc. it is nearly impossible to guarantee this. So it will be really useful to have the SVA errors accounting to simulation PASS/FAIL.Any advice on this will be appreciated.ThanksAjeetha, CVCwww.noveldv.com
You can use the 'assert -summary' TCL command to get a summary of assertion errors.assert -summary ...Print summary report of assertion statistics. -byfailure..............Sort summary by number of failures. -byname.................Sort summary by property name. -final..................Defer summary report until the end of simulation. -redirect ....Print the summary output to the file called "".
The way that we suggest in the URM is to use the included `DUT_ERROR macro. This macro displays an error message and increments an error counter. Depending on the severity level passed as an argument decides whether the simulation continues or stops.The DUT_ERROR macro and error handling tasks are contained in a urm_util package that is included with the IPCM install.Tim
I don't understand the difference between calling $error and calling `DUT_ERROR:assert(error_cond) $error;vs.assert(error_cond) `DUT_ERROR;Tim