Hi, I have OCP eVC. In my environment 3 instances of this eVC to be present. But these 3 instances will have different configuration parameters. The following the one such configuration.The default OCP signals in the eVC are defined as below: sig_Maddr : inout simple_port of uint is instance; sig_Mdata : inout simple_port of uint(bits:128) is instance;In my environment i need to constrain the above signals to be , sig_Maddr : inout simple_port of uint (bits :8 ) is instance;
sig_Mdata : inout simple_port of uint(bits: 32) is instance; How can we constrain the signals as above.-Arjun.
You do not need to change the e port declarations in the OCP eVC in order to connect it to signals that has smaller bit width. Instead you should just simply 'bind' the signals from your RTL to e port without thinking about bit width mismatch. Specman will automatically do type conversion for you.e.g.keep bind (sig_Maddr, external);keep sig_Maddr.hdl_path() == "rtl_signal_sig_Maddr";keep sig_Maddr.agent() == "Verilog";Look at the example files in /examples directory to see more examples on signal binding.
thanks for the reply.