In my design I have 2 instances of PLL. The PLL A and PLL B are identical with two output pins (synchronous outputs). I have cascaded one of the output port of PLL A to PLL B. My module top/s_inst uses two clocks one from the output of PLL A directly and another from the output of PLL B ( whose input is the cascaded to PLL A). In this case, how should I constrain my clock?
Is it OK if I define the first clock to s_inst from the output pin of PLL A and the second clock to s_inst from the output pin of PLL B.
1) Will the edges of PLL A clock and PLL B clock to s_inst be synchronozed automatically?
2) Should I consider the delay incurred by PLL B as an insertion delay or just don't care about it?
please do help on this.
1. Yeah if you donot define false between any of clocks you have defined
2.You need to consider the delay through PLL B. You can model as insertion delay.
In reply to ubbala:
the short answer is it depends on how your PLL liberty models model the PLL but in all likelyhood you will have to define not only clocks but somehow model not only insertion delay as ubbala mentioned but also things like phase offset and jittter. As mentioned, it really depends on what you are trying to accomplish, whether you are using a pre or post P&R netlist, etc. A web search for "PLL model SDC" will likely return a few good articles regarding PLL modelling techniques.
hope this helps,