When the source clock for a generated clock is from an internal module, report_timing times launch and capture off of the same edge of this generated clock. create_clock -name sclk -period 10 top/U1/U23/port2 create_generated_clock -name gclk -source sclk -divide_by 8 .... When doing timing report, the launch clock is gclk at time 0 and capture clock is gclk at time 0. So, the path always misses timing. Have anybody seen this in their design?
Do you mean report_timing in late mode or early mode? In early mode, launch and capture edge are both at 0.
Another thing to check is to use 'report_clocks -generated' to see if the phase shifts for this clock are correct.
Synthman, Thanks for the reply. Figured out that the clock should be coming from top port. So things are fine now. ;-)