Hi Everybody,I have a problem with a sdf-annotated netlist during elaboration before simulating it with ncsim. I get the following output for severall cells during elaboration:
input C,D,SN; |ncelab: *W,SDFNMX (/home/xxxxx/CORELIB_sdf3.0.v,1981|6): SDF annotation on segment 'tb_registerbank.registerbank_i.dataout_control_i.\rd_cnt_reg .C' will be ignored.
module Flip-Flop (C,D,Q,QN,SN);output Q,QN;input C,D,SN; //line 1981`ifdef functionalU_FD_P_SB_NO (buf_Q,D,C,SN,1'b1);`elsereg notifier;U_FD_P_SB_NO (buf_Q,D,C,SN,notifier);`endifbuf (Q,buf_Q);not (QN,buf_Q);`ifdef functional`else specify (posedge C => (Q:D)) = (1,1); (posedge C => (QN:D)) = (1,1); (SN => Q) = (1,1); (SN => QN) = (1,1); $setup(posedge D, posedge C, 0, notifier); $setup(negedge D, posedge C, 0, notifier); $recovery(posedge SN, posedge C, 0, notifier); $hold(posedge C, negedge D, 0, notifier); $hold(posedge C, posedge D, 0, notifier); $removal(posedge SN, posedge C, 0, notifier);// $hold(posedge C, posedge SN, 0, notifier); $width(posedge C, 1, 0, notifier); $width(negedge C, 1, 0, notifier); $width(negedge SN, 1, 0, notifier);endspecify`endifendmodule`endcelldefine
Hi, Not sure if I understood your problem well enough, but try: nchelp ncelab HTHAjeetha, CVCwww.noveldv.com
Hi PNR,Will need to look at the lines in SDF that is giving the warning (is it line 1981?). Look at the SDF, and then the lines between "spcify"/"endspecify" in the verilog model, you may figure out the issue. Possible causes are:1. separate setup and hold, or just setuphold syntax used.2. leading posedge/negedge in verilog model but not in .lib (which is used by the tool to generate the SDF).3. separate recovery/removal vs. recrem4. ??etc??Regards,Eng Han
Hi, thanks to ajeetha. The information given by nchelp for mnemonic SDFNMX:
ncelab/SDFNMX = SDF annotation is not permitted on any segment (both digital & analog) of mixed-signal. The annotated delay will be ignored, and circuit will be simulated without delay.