In my verilog code, I have XOR1 gate (in0, in1, out). Port "out" connects to the "D" input of a DFF. A code sample is below:
assign out = in0 ^ in1;
dff dff_0(.CLK(CLK), .in(out), .out(q));
module dff(CLK, in, out);
input [127:0] in;
output reg [127:0] out;
out <= in;
However, after synthesis one additional XOR2 gate is inserted between
XOR1 and DFF, i.e., "out" connects to one input of XOR2 and the output
of XOR2 connects to "D" input of the DFF. I understand that the tool is
doing some optimization related to my other logic. But how can I enforce
the gate sequence in my verilog code in this specific case? (XOR1
connect to DFF directly) I am fine with restructuring the code.
BTW: I do not use any timing constraints.