It sounds like you may be able to use a ECset that defines the delay values desired between just those two reference designators. When it applies the ECSet to the various nets using that ECSet it will try to do the matching based on refdes so that just may solve your problem. I'll assume that the bus group in question has basically the same set of connections (ie same number of pins they attach to) , if not find the bit with the most connections and extract into SigXP. Add the Set Optional pin for the extra component, Set Constraints, and select theIC100, CN100 pins enter the values desired and save the ecset back to the design. This can then be referenced by any number of nets as long as they have the similar connections. There is some good documentation on the use of ECSets in the online help.