** Dear All,**

**I am a beginner in verilogA .**

**I wrote a code but when I ran PSS it showed hidden state in the code and didn't run.**

**My behavioural model is as below:-**

// VerilogA for VERILOG_A_MODEL, HARD_LIMIT_GM, veriloga

`include "constants.vams"

`include "disciplines.vams"

module HARD_LIMIT_GM(in,out);

inout in,out;

parameter real vtrans = 0;

parameter real tdelay = 0 from [0:inf);

parameter real trise = 1p from (0:inf);

parameter real tfall = 1p from (0:inf);

parameter real Gm=-5m;

electrical in,out;

real vout_val;

analog begin

@ (cross(V(in) - vtrans, 1)) __vout_val __= 1;

@ (cross(V(in) - vtrans, -1)) __vout_val__ = 0;

I(out) <+ Gm * transition( vout_val, tdelay, trise, tfall);

end

endmodule

**Could anybody please tell how I can avoid the hidden state (vout_val ) ?**

**Kind Regards, **