I use "Pnoise jitter" to get the Jee of a PLL. The reference frequency is 20MHz, and the divider ratio is 8, (VCO frequency 160MHz). I use 1kHz as the integration lower limit, is that right? What is the integration upper limit? Is it fvco/2 = 80MHz? There are spurs at 20MHz, 40MHz and 60MHz. If the integration includes these spur frequencies, how does the infinite flick noise at these points affect the integration results?
Another question is :
When I simulate a free running VCO with Pnoise jitter analysis, the four function in the Direct Plot Form below Pnoise jitter are pnoise, -20dB..., Jc and Jcc. When I simulate a PLL, the four functions differ. There is no pnoise. What should I do if I want to look at the pnoise?