We are using an IP block from our foundry in our chip. The IP block is located below the top level of the hierarchy. And, the IP block is presented as an empty layout block, containing only pins and boundary shapes.
Currently, as we run Assura LVS with the default options, our outside connections to the IP block's pins are not verified. We can swap connections - even leave connections open - but LVS does not complain! That's no good...
What do I need to do differently to make Assura LVS verify our connections to the IP block's pins?
In reply to Quek:
Thanks for your reply. To answer your questions:
1) I cannot find the IP block's cellName even mentioned in the design.erc file.
2) The layout and schematic are both df2 - no GDS2.
3) I found the following rules in my extract.rul file:
;; ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>;; text layer ;; POLY1_pintext = textToPin( "PIN" type( "poly1")) MET1_pintext = textToPin( "PIN" type( "metal1")) MET2_pintext = textToPin( "PIN" type( "metal2")) MET3_pintext = textToPin( "PIN" type( "metal3")) MET4_pintext = textToPin( "PIN" type( "metal4")) PAD_pintext = textToPin( "PIN" type( "pad")) ;;;; symbolic pins for macro LVS and RCX;; POLY1_sympin = pinLayer( "POLY1" type( "pin")) MET1_sympin = pinLayer( "MET1" type( "pin")) MET2_sympin = pinLayer( "MET2" type( "pin")) MET3_sympin = pinLayer( "MET3" type( "pin")) MET4_sympin = pinLayer( "MET4" type( "pin")) ;; ;; >>>>>>>>>>>>>>>>>>>>>>>>>>>>>>;; pinPurpose layer (only drc) ;; POLY1_pinPurpose = layer( "POLY1" type( "pin")) MET1_pinPurpose = layer( "MET1" type( "pin")) MET2_pinPurpose = layer( "MET2" type( "pin")) MET3_pinPurpose = layer( "MET3" type( "pin")) MET4_pinPurpose = layer( "MET4" type( "pin")) PAD_pinPurpose = layer( "PAD" type( "pin"))
Using this PDK, for general pin designation, we only have to label the drawing shapes using layer, "PIN", purpose, "<metal_layer>", as indicated above. However, inside the IP block layout, the pin shape also exists as a df2 "terminal". So, it should be covered both ways.
4) The Assura version is:
$ assura -Wsub-version 3.2_USR2_HF11$ assura -V@(#)$CDS: assura version av3.2:Production:dfII5.1.41:188.8.131.520.6.130 06/29/2009 04:29 (logavt05) $
5) I have read the section you described, plus the related one in the user's guide, and I have tried the following statements in my runs:
blackBox("MY_IP_BLOCK_CELL_NAME" sch)blackBox("MY_IP_BLOCK_CELL_NAME" lay)
Strangely, both runs complain about not being able to find the cell in the design hierarchy, although I clearly see the cellName being used in both designs. ... Incidentally, for testing purposes, I am running LVS at a lower level of the chip, in which the IP block exists as a top level cell. I don't know if that makes a difference...
Maybe the extract rules need some help, since neither I nor Assura can find the cell in Assura's schematic or layout netlist?
In reply to TrevorB:
a. I tried using the syntax you suggested for ?blackBox ("cellName viewName libName"), but that did not help. LVS still passes, even though I switched two connections, deliberately testing for a fail.
BTW, my IP block does not have a schematic. We created an empty one to make LVS run to completion. Was this incorrect?
b. We do not have ?textPriOnly=t set or ?textLeve=0.0. Should we? I verified that the pins are correct in the layout. (They have drawing, pin shapes, and pin text with pin-text origin over the drawing and pin shapes.)
Should I check anything else? I am really stumped.
BTW, I could not find the blackBox syntax you mentioned in the docs. Is it documented elsewhere?
Hi TrevorA cellname can be short (simply the cellname) or long (with view and lib info). Please see the section on "Representing Cell and Device Names" in the Assura Developer's Guide. Actually the correct cmd is :blackBox("cellName viewName libName")and not:?blackBox ("cellName viewName libName")textPriOnly and textLevel need not be used if they are not necessary. I will think more about your question and update you again. Would you please uploaded your log, cls, csm and erc files? Total of 4 files.ThanksQuek
I spoke with our foundry's support team, and I experimented some more. I finally got it working. Here's what I learned:
As an example, here are the guts of our dummy schematic for the black box:
Thanks again for the help, Quek!
Hi TrevorIt is good to know that the problem has been resolved. Actually your problem no longer exists from Assura41 onwards. Prior to Assura41, it is not possible for Assura to netlist an empty schematic that has only pins. The workaround is to copy the symbol view as "auLvs" view and then change the cdf componentName (Go to cdf form, press "simInfo" button and select auLvs simulator) to the cell name. This will also work, no components are needed inside the empty schematic. Only pins are necessary. I have confirmed what you are observing using Assura32USR2.If the latest Assura41USR1_HF3 is used, it is not necessary to create the auLvs view. The empty pins-only schematic will be netlisted correctly. If you have time, maybe you can switch to Assura41USR1_HF3 and give it a try.Thank you very much for the detail explanation. I think you have contributed a valuable post to the forum which will be helpful to other users. : )Best regardsQuek
This post was really valuable. We have been running into the same problem with an empty schematic, but had not yet determined the best method for fixing this problem.
We are on Assura41USR1_HF14, and the empty pins-only schematic was still not netlisted correctly. Maybe it was there on HF3, but by the time it got to HF14, it has disappeared again.
I'm going to try the workaround for copying the symbol to the auLVS view. This will probably be the best solution for us at this time.
I tried both HF14 and creating an "auLvs" view and neither of them worked with our cell.
The symbol we use has pins that are busses for example PA<8:0>. It seems that when Assura runs, it does not recognize any pins that are labeled as busses. Is there a workaround for this?
In reply to shumble1:
Hi shumble1If you are seeing netlisting error due to bus notations for the pins, this issue has already been resolved and the fix is in Assura41USR2. USR2 is the immediate version after Assura41USR1_HF14. You can of course also use the latest version Assura41USR2_HF1. The fix is in it too. Previously Assura is unable to correctly expand a bus notation in cdf "termOrder" property and a workaround was to manually expand it in the cdf form. Eg.Original pin name in "termOrder" property in cdf form:abc<0:3>Workaround:abc<0> abc<1> abc<2> abc<3>Would you please try Assura41USR2_HF1 to see if it resolves your problem? If it does not, kindly post the Assura log file that contains the error message.ThanksQuek