Im trying to simulate an adder circuit which produces an output
depending on an 'input offset'. That is the offset gets added to itself and whenever the addition results in an overflow it
should produce an output.
The adder is a 4 bit adder and so whener the sum exceeds 1111 it shud
produce a carry out and the resulting sum shud substract 16 from itself and
produce a new sum which would then be smaller than 1111. I hope u get
I made schematic for the circuit which consists of a simple 4 bit
Ripple carry adder and a register driven by the clock because I want
the addition to take place with the clock. The output of the adder
feeds the register and the reg op feeds one of the inputs to the
adder thus creating a loop structure.
After doing that I create a symbol out of it and use it in a TB to see
After certain simulation trials of the Test bench i get this strange
error in the spectre.out file which says that "I11 instance is an
instance of an undefined model subcircuit" . Here 'I11' refers to the
instance name of the symbol I created earlier.
This strange error disappears when i make an exact copy of the same
Test Bench schematic into another schematic. And again after a while
the same error pops up and then i recreate another schematic and then
it works..which is becoming kind of annoying. Does anyone have any
pointers as to why is it happening?
Hope to get some hints about that.
This sounds a bit peculiar, but do you have the UNIX environment variable CDS_Netlisting_Mode set to "Analog"? Try typing (in the CIW):cdsGetNetlistMode()and seeing if it reports "Analog". If not, then do:setenv CDS_Netlisting_Mode Analog (if using csh)export CDS_Netlisting_Mode=Analog (if using bash or ksh)in the terminal window before starting DFII, and then seeing if that fixes it. You'll probably need to do a Simulation->Netlist->Recreate.Regards,Andrew.
Hello Andrew.Thanks for the suggestion. I tried what u said by typing the command at the ICFB window and I did see the message analog there.This does mean that I am indeed in the analog mode. Additionally when I use the simulation ->netlist recreate option I see a netlist wherein the symbol I11 in my case reads "subcircuit" instead of the name of the block which I should be seeing there.I thnk this is where the hierachy flattening stops and it doesnt go below that level and issues an error which is obvious as it cannot find the subblocks.But I do not understand what I am doing that is triggering such a strange behavior. Additionally where in the unix file structure can I find the schematic. It does show up though messed up) when I use the simulation->netlist display option bt I cannot seem to find it on the folders. Is there a way by which I can edit the schematic file manually to see if that could fix the problem.If I just change the name of the erroneous block from subcircuit to the name of the symbol which it represents keeping the case and everything, how do I get the netlister start the heirarchy flattening process from this point?Hope to hear from you guys?I can upload the whole library if u like..and if u have the time to look over!! :)...Best Regards,Aijaz.
I didn't quite understand all of what you were asking above (probably just a matter of your English).Anyway, for the instance I11, this is a symbol of a particular cell. For that cell, do you have other views along side it in the library manager? If so, what are they? (I'm assuming one is schematic, but are there any other view names?)Regards,Andrew.
Hello.The instance I11 is basically a symbol which I created from its schematic earlier using the [b] Design->Create cell view->From cell view [/b] sequence.Thus this instance I11 does have a schematic view and a symbol view and I use the symbol view in order to use it in other schematics. It this probably occuring because i havent updated the schematic view before I use the symbol view anywhere else? ...Looking for an answer from you,best regards,Aijaz.
But are there any other views other than schematic and symbol? Also, what simulator are you using in ADE? (assuming you're using Analog Design Environment). What does Setup->Environment show for the view list and stop list?Regards,Andrew.
The instance I11 referes to a circuit which has a schematic view and a symbol view. The schematic view is again composed of symbol views of other cells. The test bench in which I have instantiated that cell using the synbol (which was automatically named I11 by cadence) also has a config view in addition to the schematic view. (This is the schematic view of the test bench and is different from the schematic view of the circuit under question! )I using the spectre template in the config view so the view list is : "spectre cmos_sch schematic veriloga ahdl" for the switch view and "spectre ahdl veriloga" for the stop view list.Additionally the "use spice netlist reader" option is unchecked.I hope this information helps,Regards,Aijaz.
I can't see any reason then why this would netlist as "subcircuit". Can you post the resulting netlist? Might give me some clues...Andrew.
Hello andrew.The problem that I described happens occasionaly and right now the very same circuit seems to be doing all fine.However at certain times this problem arises and if it happens again ill surely make a note of the netlist file and post it here!Thanks for the help andrew and hope to get a good hold of cadence with the help of my peers here and at school.Best Regards,Aijaz
I think you'll probably need to contact Cadence customer support to be able to properly get to the bottom of this.Regards,Andrew.
Hello.Here I face the same problem again. Get the same message in the spectre.out window which reads Command line: /sw/cadence/IC5141_USR2/tools.lnx86/spectre/bin/32bit/spectre -env \ artist5.1.0 +escchars +log ../psf/spectre.out -format psfbin \ -raw ../psf +lqtimeout 900 +param \ /sw/cadence/libraries/ams_hit-3.70/spectre/ams_range.lmts \ input.scsLoading /sw/cadence/IC5141_USR2/tools.lnx86/cmi/lib/4.0/libinfineon_sh.so ...Loading /sw/cadence/IC5141_USR2/tools.lnx86/cmi/lib/4.0/libnortel_sh.so ...Loading /sw/cadence/IC5141_USR2/tools.lnx86/cmi/lib/4.0/libphilips_sh.so ...Loading /sw/cadence/IC5141_USR2/tools.lnx86/cmi/lib/4.0/libsparam_sh.so ...Loading /sw/cadence/IC5141_USR2/tools.lnx86/cmi/lib/4.0/libstmodels_sh.so ...spectre (ver. 5.10.41_USR2.052705 -- 27 May 2005).Includes RSA BSAFE(R) Cryptographic or Security Protocol Software from RSA Security, Inc.Simulating `input.scs' on asgard-07.edu.isy.liu.se at 3:59:06 PM, Fri Apr 13, 2007.Notice from spectre in `modn', during circuit read-in. modn.mosinsub: `jsw' has the unusual value of 130 pA/m.Notice from spectre in `modnm', during circuit read-in. modnm.mosinsub: `jsw' has the unusual value of 130 pA/m.Notice from spectre in `modpm', during circuit read-in. modpm.mosinsub: `jsw' has the unusual value of 610 pA/m.Notice from spectre in `modp', during circuit read-in. modp.mosinsub: `jsw' has the unusual value of 610 pA/m.Notice from spectre in `modnmh', during circuit read-in. modnmh.mosinsub: `jsw' has the unusual value of 130 pA/m. Further occurrences of this notice will be suppressed.Error found by spectre during circuit read-in. input.scs: I0 is an instance of an undefined model subcircuit.spectre terminated prematurely due to fatal error.Heres is the problem. I do not know what exactly is the problem which is causing this error. So im posting a gzipped version of the entire library.The schematic view of "therm_to_bin_TB" is the one which I am simulating and the one which is giving me this error. Please do have a look at the schematic. u can just untar the folder and add it as a library. Hope u can find some thing which can point us towards the exact cause of this annoying errorHope this time I have something concrete for you to have a look.Best Regards,Aijaz Baig.
I took a quick look at the data.The problem is that in your config view you have:View List: spectre cmos_sch schematic veriloga ahdlStop List: spectre cmos_sch schematic veriloga ahdlThis means that netlisting will stop expanding when it finds a schematic - which is NOT what you want. If it stops at the schematic, it will then use the CDF to decide how to netlist it, and that indicates the component name as "subcircuit". Also, you won't get the contents of the schematic netlisted.The stop list should be just "spectre" in this case. I tried this (having adjusted the data slightly as I don't have "PRIMLIB" components), and it netlisted correctly. Both therm_to_bin_TB and ADC_3bit_NEW_TB config views had the wrong stop list.This should have been fairly clear from the hierarchy editor - because there was no expansion of the hierarchy shown there, due to each instance stopping at the schematic.Regards,Andrew.
Ah!!that is something which i was overlooking. Thanks a lot andrew!!I hope to learn quite a few tricks on the forums here :)Best Regards,Aijaz