is there a way to simulate the effect of mismatch in parasitics (in
particular parasitic diodes)?
The pn junction of n-wells for PMOS are infact not in the schematic.
1) How could I get them from the extracted view?
2) How could I simulate the mismatch in those?
I don't know how to simulate the effect of this parasitics, but I know an case that have a very big leakage current, nearly 50mA.
In this case, we put some p-sub taps around NMOS, but we lost the p-well mask for the NMOS, as a result, these NMOS were bult on the P-sub instead of the Pwell, then we have a very big leakage current