What I am looking for is: starting from a design in HDL (VHDL/Verilog using Xilinx), is there any way to translate directly to layout (using Virtuoso LX )
Would greatly appreciate if anyone can share your experience or point me to relevant documents ?
Translation from HDL to layout requires logic synthesis to map to from C, behavioral or RTL constructs to a target technology library. Digital physical implementation is then used to map a gate-level netlist to layout using optimizations for area, timing, and power. For synthesis, you may find this reference useful: http://www.cadence.com/cadence/newsroom/press_releases/Pages/pr.aspx?xml=012009_c-to-silicon
Given your reference to Xilinx: http://www.xilinx.com/tools/designtools.htm