I'm trying to do a simple Spectre simulation with a few elements (symbols) from the ARM Std Cell library and I'm having some difficulties. First I just received the ARM library package and it includes (for every cell):
1. symbol view
2. cmos_sch view (with input and output pins)
3. a large common CDL netlist file (including all stdcell elements) in SPICE format
4. a large common LPE (with parasitics) netlist file (including all stdcell elements) in SPICE format
5. NO SCHEMATIC VIEW for the std cells
I can hack the netlist and make the simple simulation work (see 2 hacks below), but I don't want to do this everytime. The automatically generated Spectre netlist should look like one of the 2 netlists below (which I both hacked).I want to be able to use any symbol from the std cell library in a schematic and have a correct Spectre netlist generated.
Note: Both following netlists have been hacked and I want this to work automatically using the Virtuoso ADE interface.
-------Hacked Netlist 1 (subcircuit inserted in body, no include file)
simulator lang=spectreglobal 0 gnd vddinclude "/remote/eeserv01/software/cadence/Technology/IBM_PDK/cmrf8sf/V220.127.116.11DM/Spectre/models/allModels.scs"// Library name: ARM_ibm13rf_reg// Cell name: INVX4TF// View name: cmos_schsubcircuit INVX4TF A YM0 vdd a y vdd pfet W=2.34U L=0.12U M=1M1 y a gnd gnd nfet W=1.7U L=0.12U M=1ends INVX4TF// End of subcircuit definition.I1 (mida OUTb) INVX4TFI0 (INa mida) INVX4TFV0 (INa 0) vsource type=pwl wave=[ 0 0 2n 0 2.1n 1.2 ]
--- Hacked Netlist 2 (include file)
simulator lang=spectreglobal 0 gnd vddinclude "/remote/eeserv01/software/cadence/Technology/IBM_PDK/cmrf8sf/V18.104.22.168DM/Spectre/models/allModels.scs"include "ibm13rfvrvt.cdl" // which includes subckt def for INVX4TF
// NO cmos_sch subckt call here
// Library name: x_asd_testb// Cell name: std_cell_xx2// View name: schematicI1 (mida OUTb) INVX4TFI0 (INa mida) INVX4TFV0 (INa 0) vsource type=pwl wave=[ 0 0 2n 0 2.1n 1.2 ]
The reason why I can't get Spectre netlist 1 with ADE, is because I don't know how to insert the subckt definition automatically from the large common CDL file into the actual netlist. I've tried BlackBox netlisting and I still can't get this to work.
The reason why I can't get netlist 2 with ADE, is because when I include the large netlist file with all the subcircuits I get an error which states that the subcircuit is being 'redefined'. There are 2 identical subcircuit calls, and I can't figure out a way to remove the INVX4TF cmos_sch subrcircuit calls and keep the instances (I0 and I1) as well. The following is the netlist I normally get from the Virtuoso ADE environment:
global 0 gnd vdd
include "ibm13rfvrvt.cdl" // which includes subckt def for INVX4TF
// Library name: ARM_ibm13rf_reg
// Cell name: INVX4TF
// View name: cmos_sch
subcircuit INVX4TF A Y
M0 vdd a y vdd pfet W=2.34U L=0.12U M=1
M1 y a gnd gnd nfet W=1.7U L=0.12U M=1
// End of subcircuit definition.
I've spent a few days on this problem, but to no avail. I've tried using BlackBox properties, modifiying my .simrc file. Also, I tried creating a new au_cdl view and also tried modifying 'user properties' of the symbol and cmos_sch views. I've also exhausted all documentation and also the Cadence Sourcelink.
Please help, I don't know what to do next.
You might want to contact the foundry or fab service that you are using in this case. If you're a mosis customer they have their own message board, http://tech.groups.yahoo.com/group/MOSIS_Users_Group/.
canuck5. NO SCHEMATIC VIEW for the std cells
These libraries are front-end kits only. They do not contain layout
information, SPICE, or netlists.
Generally what you'll need to do is:
Then when you netlist in ADE, providing spectre is in the stop list, and is in the view list before cmos_sch, it will stop when it gets to the spectre view and just write out an instance, using the order from the CDF. The definition of the subckt would then only come from your included file.