It is working, just working more than you want it to ;-)
It will be using the currently active validVias constraint in the constraint group defined in Options->Editor (in the Wire Editing section). If the validVias includes the contact layer, it will connect from metal1 down into diffusion and hence under the transistor and up the other side (remember that mark net simply looks at the shapes - it doesn't have much intelligence).
You can stop this either by picking a constraint group which doesn't traverse into the diffusion/active/oxide/OD layer in the validVias/validLayers constraints, or by hitting F3 once you start Mark Net, and changing the "Via Layers used by Mark Net" to "Select Via Layers" and disabling the contact between the diffusion and metal1.
In reply to Andrew Beckett:
To add to Andrew's post, perhaps the "Stop Layers" feature can be used for this?
See solution ID: 11456360 titled "How to stop Mark Net from highlighting through gate diffusion?"
In reply to maven7783:
You can create your own constraint groups - this can be done either in the original technology library, or by using the Incremental Technology Database idea. If you "reference" the technology library rather than "attach" you can then add constraint groups in your own design library (say). You could define a constraint group and specify the validLayers and validVias, and then specify this constraint group in the Options->Editor form in the layout editor. Or set that via the cdsenv settings:
layout setupConstraintGroup string "virtuosoDefaultExtractorSetup"layout wireConstraintGroup string "virtuosoDefaultSetup"
Set them to whatever you've called your constraint group.
That way you shouldn't have to reset it every time you use mark net.
Probably you should search in cdnshelp for "validLayers" and "validVias" and "mark net".